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enhanced a/d flash 8-bit mcu HT66F0172/ht66f0174 revision: v1.00 date: ???? 11? ?01? ???? 11? ?01?
rev. 1.00 ? ???? 11? ?01? rev. 1.00 ? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu table of contents eates cpu feat?res ......................................................................................................................... 6 periphera? feat?res ................................................................................................................. 6 genera? description ........................................................................................ 7 se?ection tab?e ................................................................................................. 7 b?ock diagram .................................................................................................. 8 pin assignment ................................................................................................ 8 pin descriptions .............................................................................................. 9 abso??te maxim?m ratings ........................................................................... 11 d.c. characteristics ........................................................................................ 11 a.c. characteristics ....................................................................................... 1? a/d converter characteristics ...................................................................... 14 lvd&lvr e?ectrica? characteristics ............................................................ 15 power on reset e?ectrica? characteristics .................................................. 15 s?stem architect?re ...................................................................................... 16 c?ocking and pipe?ining ......................................................................................................... 16 program co?nter ................................................................................................................... 17 stack ..................................................................................................................................... 18 arithmetic and logic unit C alu ........................................................................................... 18 f?ash program memor? ................................................................................. 19 str?ct?re ................................................................................................................................ 19 specia? vectors ..................................................................................................................... 19 look-? p tab?e ........................................................................................................................ 19 tab ?e program examp?e ........................................................................................................ ?0 in circ?it programming ......................................................................................................... ?1 on-chip deb?g s?pport C ocds ......................................................................................... ?? ram data memor? ......................................................................................... ?? str?ct?re ................................................................................................................................ ?? specia? f?nction register description ........................................................ ?4 indirect addressing registers C iar0 ? iar1 ......................................................................... ?4 memor? pointers C mp0? mp1 .............................................................................................. ?4 bank pointer C bp ................................................................................................................. ?5 acc?m?? ator C acc ............................................................................................................... ?5 program co?nter low register C pcl .................................................................................. ?5 look-? p tab? e registers C tblp ? tbhp ? tblh ..................................................................... ?5 stat? s register C status .................................................................................................... ?6
rev. 1.00 ? ???? 11? ?01? rev. 1.00 ? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu eeprom data memory (only for ht66f0174) ............................................. 28 eeprom data memor? str?ct?re ........................................................................................ ?8 eeprom registers .............................................................................................................. ?8 reading data from the eeprom ........................................................................................ ?0 writing data to the eeprom ................................................................................................ ?0 write protection ..................................................................................................................... ?0 eeprom interr?pt ................................................................................................................ ?0 programming considerations ................................................................................................ ?1 oscillator ........................................................................................................ 32 osci??ator overview ............................................................................................................... ?? system clock confgurations ................................................................................................ ?? externa? cr?sta?/ceramic osci??ator C hxt ........................................................................... ?? interna? rc osci??ator C hirc ............................................................................................... ?4 externa? ?? .768 khz cr?sta? osci??ator C l xt ........................................................................ ?4 l xt osci ??ator low power f?nction ...................................................................................... ?5 interna? ??khz osci??ator C lirc ........................................................................................... ?5 s?pp?ementar? c?ocks .......................................................................................................... ?5 operating modes and system clocks ......................................................... 36 s?stem c?ocks ...................................................................................................................... ?6 s?stem operation modes ...................................................................................................... ?7 contro? register .................................................................................................................... ?8 fast wake- ?p ........................................................................................................................ 40 operating mode switching ................................................................................................... 40 normal mode to slow mode switching ........................................................................... 41 slow mode to normal mode switching .......................................................................... 41 entering the sleep 0 mode .................................................................................................. 4? entering the sleep 1 mode .................................................................................................. 4? entering the idle0 mode ...................................................................................................... 4? entering the idle1 mode ...................................................................................................... 44 standb? c?rrent considerations ........................................................................................... 44 wake- ?p ............................................................................................................................... 45 programming considerations ................................................................................................ 45 watchdog timer ............................................................................................. 46 watchdog timer c ?ock so?rce .............................................................................................. 46 watchdog timer contro ? register ......................................................................................... 46 watchdog timer operation ................................................................................................... 47 reset and initialisation .................................................................................. 48 reset f?nctions .................................................................................................................... 48 reset initia? conditions ......................................................................................................... 51
rev. 1.00 4 ???? 11? ?01? rev. 1.00 5 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu input/output ports ......................................................................................... 53 p???-high resistors ................................................................................................................ 5? port a wake- ?p ..................................................................................................................... 54 i/o port contro? registers ..................................................................................................... 55 i/o pin str?ct?res .................................................................................................................. 56 programming considerations ................................................................................................ 57 timer modules C tm ...................................................................................... 58 introd?ction ........................................................................................................................... 58 tm operation ........................................................................................................................ 58 tm c?ock so?rce ................................................................................................................... 58 tm interr?pts ......................................................................................................................... 59 tm externa? pins ................................................................................................................... 59 tm inp?t/o?tp?t pin contro? registers ................................................................................. 59 programming considerations ................................................................................................ 60 periodic type tm C ptm ................................................................................ 61 periodic tm operation .......................................................................................................... 61 periodic t ? pe tm register description ................................................................................. 6? periodic t ? pe tm operating modes ...................................................................................... 66 compare match o?tp?t mode ............................................................................................... 66 timer/co ?nter mode ............................................................................................................. 69 pwm o?tp?t mode ................................................................................................................ 69 sing?e p??se mode ................................................................................................................ 70 capt?re inp?t mode .............................................................................................................. 71 analog to digital converter .......................................................................... 73 a/d overview ........................................................................................................................ 7? a/d converter register description ...................................................................................... 7? a/d converter data registers C adrl ? adrh ..................................................................... 74 a/d converter contro? registers C adcr0? adcr1? a cerl ............................................... 74 a/d operation ....................................................................................................................... 77 a/d inp?t pins ....................................................................................................................... 78 s?mmar? of a/d conversion steps ....................................................................................... 79 programming considerations ................................................................................................ 80 a/d transfer f ?nction ........................................................................................................... 80 a/d programming examp?es ................................................................................................. 81
rev. 1.00 4 ???? 11? ?01? rev. 1.00 5 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu interrupts ........................................................................................................ 83 interr?pt registers ................................................................................................................. 8? interr?pt operation ................................................................................................................ 88 externa? interr?pt .................................................................................................................. 89 time base interr ?pt ............................................................................................................... 90 m??ti-f?nction interr?pt .......................................................................................................... 91 a/d converter interr?pt ......................................................................................................... 9? tm interr?pt ........................................................................................................................... 9? eeprom interr?pt (on?? for ht66f017?) ............................................................................ 9? lvd interr ?pt ......................................................................................................................... 9? interr? pt wake-?p f?nction .................................................................................................. 9? programming considerations ................................................................................................ 9? low voltage detector C lvd ......................................................................... 94 lvd register ......................................................................................................................... 94 lvd operation ....................................................................................................................... 95 confguration option ..................................................................................... 96 application circuits ....................................................................................... 96 instruction set ................................................................................................ 97 introd?ction ........................................................................................................................... 97 instr? ction timing .................................................................................................................. 97 moving and transferring data ............................................................................................... 97 arithmetic operations ............................................................................................................ 97 logica? and rotate operation ............................................................................................... 98 branches and contro? transfer ............................................................................................. 98 bit operations ....................................................................................................................... 98 tab ?e read operations ......................................................................................................... 98 other operations ................................................................................................................... 98 instr?ction set s?mmar? ....................................................................................................... 99 instruction defnition ................................................................................... 101 package information .................................................................................... 110 ? 0-pin dip (?00mi?) o?t?ine dimensions .............................................................................. 111 ? 0-pin sop (?00mi?) o?t?ine dimensions ............................................................................ 11 ? ? 0-pin ssop (150mi?) o?t?ine dimensions .......................................................................... 114
rev. 1.00 6 ???? 11? ?01? rev. 1.00 7 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu features cpu features ? operating voltage: f sys = 8mhz: 2.2v~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20 mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? four o scillators: external crystal C hxt external 32.768khz crystal- lxt (only for ht66f0174) internal rc C hirc internal 32khz C lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 8mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 8-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 2k16 ? ram data memory: 1288 ? eeprom memory: 648 (only for ht66f0174) ? watchdog timer function ? 18 bidirectional i/o lines ? two pin-shared external interrupts ? two 10-bit ptm ? dual time-base function for generation of fxed time interrupt signal ? 8-channel 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? package types: 20-pin dip/sop/ssop
rev. 1.00 6 ???? 11? ?01? rev. 1.00 7 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu general description the devices are flash memory type 8-bit high performance risc architecture microcontrollers. offering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter function. extremely fexible timer modules provide timing, pulse generation and pwm generation functions. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt, lxt, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimize power consumption. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure that the devices will fnd excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. selection table most features are common to all devices. the following table summarises the main features of each device. part no. vdd oscillator rom ram eeprom i / o ext. int. a/d stack time base comparator package ht66f0174 ?.?v~ 5.5v hxt hirc lirc lxt ? k1 6 1?8 8 64 8 18 ? 1?-bit8 8 ?0dip/ sop/ssop ht66f017? ?.?v~ 5.5v hxt hirc lirc ?k1 6 1?8 8 18 ? 1?-bit8 8 ?0dip/ sop/ssop
rev. 1.00 8 ???? 11? ?01? rev. 1.00 9 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu block diagram
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? ? ? ? ? ? ? ?- note: there are not lxt oscillator and eeprom in HT66F0172. pin assignment ht 66 f 0174 20 dip - a / sop - a / ssop - a 1 ? ? 4 5 6 7 8 9 ?0 19 18 17 16 15 14 1? 1? 11 10 vdd & avdd p b 0 / int 0 / an 0 / xt 1 p b 1 / int 1 / an 1 / xt ? pb ? / tck 0 / an ? pa 4 / tck 1 / an ? pa 5 / an 4 / vref p a 6 / an 5 p a 7 / tp 1 / an 6 p b ? / an 7 p b 4 / clo vss & avss pc 0 / osc 1 pc 1 / osc ? pc ? pa 0 / tp 0 / icpda / ocdsda p a 1 pa ? / icpck / ocdsck p a ? p b 6 p b 5
rev. 1.00 8 ???? 11? ?01? rev. 1.00 9 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu ht 66 f 0172 20 dip - a / sop - a / ssop - a 1 ? ? 4 5 6 7 8 9 ?0 19 18 17 16 15 14 1? 1? 11 10 vdd & avdd p b 0 / int 0 / an 0 p b 1 / int 1 / an 1 pb ? / tck 0 / an ? pa 4 / tck 1 / an ? pa 5 / an 4 / vref p a 6 / an 5 p a 7 / tp 1 / an 6 p b ? / an 7 p b 4 / clo vss & avss pc 0 / osc 1 pc 1 / osc ? pc ? pa 0 / tp 0 / icpda / ocdsda p a 1 pa ? / icpck / ocdsck p a ? p b 6 p b 5 note: 1. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the "/" sign can be used for higher priority 2. vdd&avdd means the vdd and avdd are the double bonding. 3. vss&avss means the vss and avss are the double bonding. pin descriptions with the exception of the power pins, all pins on these devices can be referenced by their port name, e.g. pa.0, pa.1etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, timer module pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pin name function op i/t o/t description pa0/tp0/ icpda/ ocdsda pa0 pawu papu st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p. tp0 tmpc cmos tm0 o?tp?t icpda st cmos icp data/address ocdsda st cmos ocds data/address? for ev chip on?? pa1 pa1 papu pawu st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p. pa ?/icpck /ocdsck pa ? papu pawu st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p. icpck st icp c ?ock pin ocdsck st ocds c?ock pin? for ev chip on?? pa ? pa ? papu pawu st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p. pa4/tck1/ an? pa4 papu pawu st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p. tck1 tm1c0 st tm1 c?ock inp?t an? acerl an a/d channe? ? pa5/an4/ vref pa5 papu pawu st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p. an4 acerl an a/d channe? 4 vref adcr1 an a/d converter reference inp?t
rev. 1.00 10 ???? 11? ?01? rev. 1.00 11 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu pin name function op i/t o/t description pa6/an5 pa6 papu pawu st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p. an5 acerl an a/d channe? 5 pa7/tp1/ an6 pa7 papu pawu st cmos genera? p?rpose i/o. register enab?ed p???-?p and wake-?p. tp1 tmpc cmos tm1 o?tp?t an6 acerl an a/d channe? 6 pb0/int0/ an0/xt1 pb0 pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p int0 intc0 integ st externa? interr?pt 0 an0 acerl an a/d channe? 0 xt1 co lxt lxt osci ??ator pin pb1/int1/ an1/xt? pb1 pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p. int1 intc? integ st externa? interr?pt 1 an1 arerl st a/d channe? 1 xt? co lxt lxt osci ??ator pin pb?/tck0/ an? pb? pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p. tck0 tm0c0 st tm0 c?ock inp?t an? acerl an a/d channe? ? pb?/an7 pb? pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p. an7 acerl an a/d channe? 7 pb4/clo pb4 pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p. clo tmpc cmos s?stem c?ock o?tp?t pb5 pb5 pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p. pb6 pb6 pbpu st cmos genera? p?rpose i/o. register enab?ed p???-?p. pc0/osc1 pc0 pcpu st cmos genera? p?rpose i/o. register enab?ed p???-?p. osc1 co hxt hxt osci ??ator pin pc1/osc? pc1 pcpu st cmos genera? p?rpose i/o. register enab?ed p???-?p. osc? co hxt hxt osci ??ator pin pc? pc? pcpu st cmos genera? p?rpose i/o. register enab?ed p???-?p. vss vss pwr negative power s?pp ??? gro?nd avss avss pwr gro? nd connection for a/d converter. vdd vdd pwr positive power s?pp?? avdd avdd pwr positive power s?pp?? for a/d converter. note : i/t: input type; o/t: output type. op: optional by confguration option (co) or register option. pwr: power; st: schmitt trigger input. cmos: cmos output; an: analog input pin. hxt: high frequency crystal oscillator . lxt: low frequency crystal oscillator .
rev. 1.00 10 ???? 11? ?01? rev. 1.00 11 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu absolute maximum ratings supply voltage ................................................................................................ v ss ?0.3v to v ss +6.0v input voltage .................................................................................................. v ss ? 0.3v to v dd +0.3v storage temperature .................................................................................................... -50 ? c to 150?c operating temperature .................................................................................................. -40 ? c to 85 ? c i oh total .................................................................................................................................. -100ma i ol total ................................................................................................................................... 100ma total power dissipation ........................................................................................................ 500mw note: these are stress ratings only. stresses exceeding the range specified under "absolute maximum ratings" may cause substantial damage to these devices. functional operation of these devices at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect devices reliability. d.c. characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating vo ?tage (hxt ? hirc) f sys = 8m hz ?.? 5.5 v f sys = 1?m hz ?.7 5.5 v f sys = ?0m hz 4.5 5.5 v i dd 1 operating c?rrent norma? mode? f sys =f h ( hxt ) ? v no ?oad? f h = 4 mhz? adc off? wdt enab ?e 0.7 1.1 ma 5v 1.8 ?.7 ma ? v no ?oad? f h = 8 mhz? adc off? wdt enab ?e 1.0 1.5 ma 5v ?.5 4.0 ma ? v no ?oad? f h = 1? mhz? adc off? wdt enab ?e 1.5 ?.5 ma 5v ?.5 5.5 ma ? v no ?oad? f h = 16 mhz? adc off? wdt enab ?e ?.0 ?.0 ma 5v 4.5 7.0 ma 5v no ?oad? f h = ?0 mhz? adc off? wdt enab ?e 5.5 8.5 ma i dd ? operating c?rrent norma? mode? f sys =f h ( hirc ) ? v no ?oad? f h = 8 mhz? adc off? wdt enab ?e ?.0 ?.8 ma 5v ?.0 4.5 ma i dd ? operating c?rrent s?ow mode? f sys =f l =f lxt f sub =lxt ? v no ?oad? f sys =lxt ? adc off ? wdt enab ?e ? lxtlp=0 10 ?0 5v ?0 50 ? v no ?oad? f sys =lxt ? adc off ? wdt enab ?e ? lxtlp=1 10 ?0 5v 40 60 i dd 4 operating c?rrent s?ow mode? f sys =f l =f lirc f sub =lirc ? v no ?oad? f sys =lirc? adc off ? wdt enab ?e 10 ?0 5v ?0 50
rev. 1.00 1? ???? 11? ?01? rev. 1.00 1? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu symbol parameter test conditions min. typ. max. unit v dd conditions i dd 5 operating c?rrent norma? mode? f h =8mhz ( hirc ) ? v no ?oad? f sys = f h /? ? adc off? wdt enab ?e 1.7 ?.4 ma 5v ?.6 4.4 ma ? v no ?oad? f sys = f h /4 ? adc off? wdt enab ?e 1.6 ?.4 ma 5v ?.4 4.0 ma ? v no ?oad? f sys = f h /8 ? adc off? wdt enab ?e 1.5 ?.? ma 5v ?.? ?.6 ma ? v no ?oad? f sys = f h /16 ? adc off? wdt enab ?e 1.4 ?.0 ma 5v ?.0 ?.? ma ? v no ?oad? f sys = f h /?? ? adc off? wdt enab ?e 1.? 1.8 ma 5v 1.8 ?.8 ma ? v no ?oad? f sys = f h /64 ? adc off? wdt enab ?e 1.? 1.6 ma 5v 1.6 ?.4 ma i idle01 idle0 mode standb? c?rrent (lxt on) ? v no ?oad? adc off? wdt enab ?e ? lxtlp=0 5 10 a 5v 16 ?? a ? v no ?oad? adc off? wdt enab ?e ? lxtlp=1 5 10 a 5v 16 ?? a i idle0? idle0 mode standb? c?rrent (lirc on) ? v no ?oad? adc off? wdt enab ?e ? lvr disab?e 1.? ?.0 a 5v ?.? 5.0 a i idle0? idle0 mode standb? c?rrent (lxt and lirc on) ? v no ?oad? adc off? wdt enab ?e ? lxtlp=0 6 1? a 5v 18 ?6 a ? v no ?oad? adc off? wdt enab ?e ? lxtlp=1 6 1? a 5v 18 ?6 a i idle11 idle1 mode standb? c?rrent (hxt on) ? v no ?oad? adc off? wdt enab ?e ? f sys = 4mhz on 0.4 0.8 ma 5v 0.8 1.6 ma i idle1? idle1 mode standb? c?rrent (hxt on) ? v no ?oad? adc off? wdt enab ?e ? f sys = 8 mhz on 0.5 1.0 ma 5v 1.0 ?.0 ma i idle1?a idle1 mode standb? c?rrent (hirc on) ? v no ?oad? adc off? wdt enab ?e ? f sys = 8 mhz on 0.8 1.6 ma 5v 1.0 ?.0 ma i idle1? idle1 mode standb? c?rrent (hxt on) ? v no ?oad? adc off? wdt enab ?e ? f sys = 1? mhz on 0.6 1.? ma 5v 1.? ?.4 ma i idle14 idle1 mode standb? c?rrent (hxt on) ? v no ?oad? adc off? wdt enab ?e ? f sys = 16 mhz on 1.0 ?.0 ma 5v ?.0 4.0 ma i idle15 idle1 mode standb? c?rrent (hxt on) 5 v no ?oad? adc off? wdt enab ?e ? f sys = ?0 mhz on ?.5 5.0 ma i sleep0 sleep0 mode standb? c?rrent (lirc off) ? v no ?oad? adc off? wdt dis ab?e ? lvr disab?e 0.1 1.0 a 5v 0.? ?.0 a i sleep11 sleep1 mode standb? c?rrent (lxt on) ? v no ?oad? adc off? wdt en ab?e ? lxtlp=0? lvr disab?e 5 10 a 5v 16 ?? a i sleep1? sleep1 mode standb? c?rrent (lxt on) ? v no ?oad? adc off? wdt en ab?e ? lxtlp=1? lvr disab?e 5 10 a 5v 15 ?0 a i sleep1? sleep1 mode standb? c?rrent (lirc on) ? v no ?oad? adc off? wdt en ab?e ? lvr disab ?e 1.? 5.0 a 5v ?.? 10 a v il inp? t low vo?tage for i/o ports? or inp?t pins 5v 0 1.5 v 0 0. ? v dd v v ih inp? t high vo?tage for i/o ports? or inp?t pins 5v ?.5 5.0 v 0. 8 v dd v dd v
rev. 1.00 1? ???? 11? ?01? rev. 1.00 1? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu symbol parameter test conditions min. typ. max. unit v dd conditions i ol i/o port sink c?rrent ? v v ol =0.1v dd 4 8 ma 5v v ol =0.1v dd 10 ?0 ma i oh i/o port so?rce c?rrent ? v v oh =0.9v dd -? -4 ma 5v v oh =0.9v dd -5 -10 ma r ph p???-high resistance for i/o ports ? v ?0 60 100 k 5v 10 ?0 50 k a.c. characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu operating c?ock ?.? v~5.5v dc 8 mhz ?.7 v~5.5v dc 1? mhz 4.5 v~5.5v dc ?0 mhz f sys s?stem c?ock (h xt ) ?.? v~5.5v 0.4 8 mhz ?.7 v~5.5v 0.4 1? mhz 4.5 v~5.5v 0.4 ?0 mhz f hirc s?stem c?ock ( hirc ) ?v/5v ta = ?5c -?% 8 ?% mhz ?v/5v ta = 0c ~ 70 c -5% 8 5% mhz ?.? v~5.5v ta = 0c ~ 70 c -7% 8 7% mhz ?.? v~5.5v ta = -40c ~ 85c -10% 8 10% mhz f lirc s?stem c?ock ( lirc ) 5v ta = ?5c -10% ?? +10% khz ?.?v~5.5v ta = -40c ~ 85c -?0% ?? +60% khz t timer tckn inp?t p??se width 0.? s t int interr?pt p??se width 1 0 s t eerd eeprom read time ? 4 t sys t eewr eeprom write time ? 4 ms t sst s?stem start-? p timer period (power on reset) 1 ?8 t sys s?stem start-? p timer period (wake- ? p from halt ? f sys off at halt state) f sys =hirc 16 s?stem start-? p timer period (wake- ? p from halt ? f sys off at halt state) f sys = l irc ? s?stem start-? p timer period (wake- ? p from halt ? f sys on at halt state) ? t rstd s?stem reset de?a? time (power on reset? lvr reset? lvr s/w reset (lvrc) ? wdt s/w reset (wdtc)) ?5 50 100 ms s?stem reset de?a? time (wdt norma ? reset) 8.? 16.7 ??.? ms 1rwhw sys i sys r pdd dffudf ri ud rfdru iuf d frs fdsdfru r efrfe d drfddfrryfdsre
rev. 1.00 14 ???? 11? ?01? rev. 1.00 15 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu a/d converter characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd condition av dd a/d converter operating vo ?tage ?.7 5.5 v v adi a/d converter inp? t vo?tage 0 v ref ma v ref a/d converter reference vo ?tage ? av dd v v bg reference vo ?tage with b? ffer vo?tage -?% 1.?5 +?% v dnl 1 differentia ? n on-?inearit? ?.7v v ref =av dd =v dd t adck =0.5s ta=25?c -? +? lsb ?v 5v dnl ? differentia ? n on-?inearit? ?.7v v ref =av dd =v dd t adck =0.5s ta=-40?c ~ 85?c -4 +4 lsb ?v 5v inl 1 integra? n on-?inearit? ?.7v v ref =av dd =v dd t adck =0.5s ta=25?c -4 +4 lsb ?v 5v inl ? integra? n on-?inearit? ?.7v v ref =av dd =v dd t adck =0.5s ta=-40?c ~ 85?c -8 +8 lsb ?v 5v i adc additiona? power cons?mption if a/d converter is ? sed ?v no ?oad (t adck =0.5s ) 0.9 1.?5 ma 5v 1.? 1.8 ma i bg additiona? power cons?mption if v bg reference with b? ffer is ?sed ?00 ?00 a t adck a/d converter c?ock period 0.5 10 s t adc a/d conversion time (inc??de samp?e and ho? d time) 1? bit adc 16 t adck t ads a/d converter samp? ing time 4 t adck t on?st a/d converter on-to-start time ? s t bgs v bg t ?rn on stab? e time ?00 s
rev. 1.00 14 ???? 11? ?01? rev. 1.00 15 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu lvd&lvr electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr1 low vo ? tage reset vo?tage lvr enab ?e? ?.10v option -5% ?.10 +5% v v lvr ? lvr enab ?e? ?.55v option ?.55 v v lvr ? lvr enab ?e? ?.15v option ?.15 v v lvr4 lvr enab ?e? ?.80v option ?.80 v v lvd1 low vo ? tage detector vo?tage lvden=1 ? v lvd =?. 0 v -5% ?.00 +5% v v lvd ? lvden=1 ? v lvd =?.?v ?.?0 v v lvd ? lvden=1 ? v lvd =?.4v ?.40 v v lvd4 lvden=1 ? v lvd =?.7v ?.70 v v lvd5 lvden=1 ? v lvd =?.0v ?.00 v v lvd6 lvden=1 ? v lvd =?.?v ?.?0 v v lvd7 lvden=1 ? v lvd =?.6v ?.60 v v lvd8 lvden=1 ? v lvd =4.0v 4.00 v i lvr additiona? power cons?mption if lvr is used ?v lvr disab ?e lvr enab ?e ?0 45 a 5v 60 90 a i lv d additiona? power cons?mption if lvd is used ?v lv d disab?e lv d enab?e (lvr disab ?e) 40 60 a 5v 75 115 a ?v lv d disab?e lv d enab?e (lvr enab ?e) ?0 45 a 5v 60 90 a t lvr low vo ?tage width to reset 1?0 ?40 480 s t lv d low vo ?tage width to interr?pt ?0 45 90 s t lv ds lvdo stab ?e time lv d off lv d on (lvr enab ?e or disab?e) 15 s t sreset software reset width to reset 45 90 1?0 s power on reset electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd condition v por v dd start vo ?tage to ens?re power-on reset 100 mv rr vdd v dd rise rate to ens?re power-on reset 0.0?5 v/ms t por power-on reset low p??se width witho?t 0.1f between vdd and vss ? s with 0.1f between vdd and vss 1 0 s
rev. 1.00 16 ???? 11? ?01? rev. 1.00 17 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the device takes advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility. this makes the device suitable for low- cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from hxt, lxt, hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? ? ? ? system clock and pipelining
rev. 1.00 16 ???? 11? ?01? rev. 1.00 17 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ?? ? ? - ? ? ? ? ? ? ? ? ? -? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as "jmp" or "call" that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc10~pc8 pcl7~pcl0 the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 18 ???? 11? ?01? rev. 1.00 19 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.00 18 ???? 11? ?01? rev. 1.00 19 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu flash program memory the program memory is the location where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, this flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 2k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupts entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. 000 h reset interr?pt vector 004 h 0?4 h 7 ffh 16 bits program memory structure special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the "tabrd[m]" or "tabrdl[m]" instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as "0". the accompanying diagram illustrates the addressing data fow of the look-up table.

rev. 1.00 ?0 ???? 11? ?01? rev. 1.00 ?1 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrd [m] @10 @9 @8 @7 @6 @5 @4 @? @? @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @? @? @1 @0 table location note: b10~b0: table location bits @7~@0: table pointer (tblp) bits @10~@8: table pointer (tbhp) bits table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "700h" which refers to the start address of the last page within the 2k words program memory of the device. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "706h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,07h ; initialise high table pointer mov tbhp,a : : t abrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "706h" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "705h" transferred to tempreg2 and tblh in this ; example the data "1ah" is transferred to tempreg1 and data "0fh" to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.00 ?0 ???? 11? ?01? rev. 1.00 ?1 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to writer programming pin correspondence table is as follows: holtek write pins mcu programming pins function icpda pa0 programming seria? data/address icpck pa ? programming seria? c?ock vdd vdd power s?pp?? vss vss gro?nd during the programming process, the user must there take care to ensure that no other outputs are connected to these two pins. the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature.
note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf.
rev. 1.00 ?? ???? 11? ?01? rev. 1.00 ?? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu on-chip debug support C ocds an ev chip exists for the purposes of device emulation. this ev chip device also provides an "on-chip debug" function to debug the device during the development process. the ev chip and the actual mcu device are almost functionally compatible except for the "on-chip debug" function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the actual mcu device will have no effect in the ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp. for a more detailed ocds description, refer to the corresponding document named "holtek e-link for 8-bit mcu ocds users guide". holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip deb?g s?pport data/address inp?t/o?tp?t ocdsck ocdsck on-chip deb?g s?pport c?ock inp?t vdd vdd power s?pp?? gnd vss gro?nd ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. the ram data memory capacity is 128 8 bits. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. capacity banks 1?8 8 0: 80h~ffh
rev. 1.00 ?? ???? 11? ?01? rev. 1.00 ?? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu 00 h iar 0 01 h mp 0 0? h iar 1 0? h mp 1 04 h 05 h acc 06 h pcl 07 h tblp 08 h tblh 09 h tbhp 0 ah status 0 bh smod 0 ch lvdc 0 dh integ 0 eh wdtc 0 fh tbc 10 h intc 0 11 h intc 1 1? h 19 h pcpu 18 h pawu 1 bh 1 ah 1 dh 1 ch 1 fh pa pac 1 eh ?5 h ?6 h ?9 h ?8 h ? bh ? ch ? dh ?5 h tm 1 c 1 ?4 h tm 1 c 0 ?6 h tm 1 dh tm 1 dl tm 1 ah tm 1 al ?7 h ? ah read 0 on?? ? bh ? ch bp 1? h 14 h mfi 0 15 h mfi 1 16 h 17 h ? fh tm 0 c 1 ? eh tm 0 c 0 ?0 h ?? h tm 0 dh ?1 h tm 0 dl tm 0 ah ?? h tm 0 al : un?sed ? read as 00 h intc ? mfi ? un?sed un?sed eea eed pcpu pb pbc ?7 h un?sed ? ah tm 0 rpl tm 1 rpl ? dh ? eh un?sed ? fh eec bank 0 bank 1 bank 0 bank 1 tmpc ctrl lvrc pc ?8 h ?9 h pcc adrh adrl adcr 0 adcr 1 acerl ?? h ?? h ?4 h ?0 h ?1 h un?sed un?sed tm 0 rph tm 1 rph pbpu 40 h 7 fh ht 66 f 0174 00 h iar 0 01 h mp 0 0? h iar 1 0? h mp 1 04 h 05 h acc 06 h pcl 07 h tblp 08 h tblh 09 h tbhp 0 ah status 0 bh smod 0 ch lvdc 0 dh integ 0 eh wdtc 0 fh tbc 10 h intc 0 11 h intc 1 1? h 19 h pcpu 18 h pawu 1 bh 1 ah 1 dh 1 ch 1 fh pa pac 1 eh ?5 h ?6 h ?9 h ?8 h ? bh ? ch ? dh ?5 h tm 1 c 1 ?4 h tm 1 c 0 ?6 h tm 1 dh tm 1 dl tm 1 ah tm 1 al ?7 h ? ah read 0 on?? ? bh ? ch bp 1? h 14 h mfi 0 15 h mfi 1 16 h 17 h ? fh tm 0 c 1 ? eh tm 0 c 0 ?0 h ?? h tm 0 dh ?1 h tm 0 dl tm 0 ah ?? h tm 0 al : un?sed ? read as 00 h intc ? mfi ? un?sed un?sed pcpu pb pbc ?7 h un?sed ? ah tm 0 rpl tm 1 rpl ? dh ? eh un?sed ? fh bank 0 bank 1 bank 0 bank 1 tmpc ctrl lvrc pc ?8 h ?9 h pcc adrh adrl adcr 0 adcr 1 acerl ?? h ?? h ?4 h ?0 h ?1 h un?sed un?sed tm 0 rph tm 1 rph pbpu 40 h 7 fh un?sed un?sed ht 66 f 017 2 data memory structure the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h.
rev. 1.00 ?4 ???? 11? ?01? rev. 1.00 ?5 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu special function register description most of the special function register details will be described in the relevant functional section s , however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start : mov a , 04h ; setup size of block mov block , a mov a , offset adres1 ; accumulator loaded with frst ram address mov mp0 , a ; setup memory pointer with frst ram address loop : clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.00 ?4 ???? 11? ?01? rev. 1.00 ?5 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu bank pointer C bp for this device, the data memory is divided into two banks, bank0 and bank1. selecting the required data memory area is achieved using the bank pointer. bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from bank1 must be implemented using indirect addressing. bp register bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 bit 7 ~ 1 unimplemented, read as "0" bit 0 dmbp0: select data memory banks 0: bank 0 1: bank 1 accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointers and indicate the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.00 ?6 ???? 11? ?01? rev. 1.00 ?7 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the "clr wdt" or "halt" instruction. the pdf fag is affected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "halt" instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.00 ?6 ???? 11? ?01? rev. 1.00 ?7 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "" ?nknown bit 7 ~ 6 unimplemented, read as "0" bit 5 to: watchdog time-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf: power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 ?8 ???? 11? ?01? rev. 1.00 ?9 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu eeprom data memory (only for ht66f0174) one of the special features in the device is its internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 648 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly accessible in the same way as the other types of memory. instead it has to be accessed indirectly through the eeprom control registers. eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special function register. the eec register however, being located in bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d5 d4 d? d? d1 d0 eed d7 d6 d5 d4 d? d? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 ~ 0 d 5~d0: data eeprom address data eeprom address bit 5 ~ bit 0
rev. 1.00 ?8 ???? 11? ?01? rev. 1.00 ?9 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 d7~d0: data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as "0" bit 3 wren: data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr: eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren has not frst been set high. bit 1 rden: data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd: eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to "1" at the same time in one instruction. the wr and rd can not be set to "1" at the same time.
rev. 1.00 ?0 ???? 11? ?01? rev. 1.00 ?1 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register. to write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also frst be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program.
rev. 1.00 ?0 ???? 11? ?01? rev. 1.00 ?1 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly. the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. programming examples ? reading data from the eeprom - polling method 029((3520b5(6 xvhughhgdgguhvv 029(( 029 vhwxsphprusrlwhu03 02903 03srlwvwr((&uhjlvwhu 029 vhwxsdn3rlwhu 0293 6(7,5 vhw5(1elwhdeohuhdgrshudwlrv 6(7,5 vwduw5hdg&fohvhw5elw back: 6,5 fkhfhdffhh -03. /5,5 ldeh3520lh /53 02 hhdddhlh 025b7 ? writing data to the eeprom - polling method 029((3520b5(6 xvhughhgdgguhvv 029(( 029((3520b7 xvhughhggdwd 029(( 029 vhwxsphprusrlwhu03 02903 03srlwvwr((&uhjlvwhu 029 vhwxsdn3rlwhu 0293 &/5(0, 6(7,5 vhw:5(1elwhdeohzulwhrshudwlrv 6(7,5 vwduw:ulwh&fohvhw:5elw 6(7(0, back: 6,5 fkhflhffhh -03. /5,5 ldeh3520lh /53
rev. 1.00 ?? ???? 11? ?01? rev. 1.00 ?? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. external oscillators requiring some external components as well as f ully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. type name freq. pins externa? cr?sta? hxt 400khz~?0mhz osc1/osc? interna? high speed rc hirc 8mhz externa? low speed cr?sta? lxt ??.768khz xt1/xt? interna? low speed rc lirc ??khz oscillator types system clock confgurations there are four methods of generating the system clock, high speed oscillators and low speed oscillators. the high speed oscillators are the external crystal/ ceramic oscillator and the internal 8mhz rc oscillator. the low speed oscillator is the internal 32khz (lirc) oscillator and the external 32.768khz crystal oscillator. note that there isn't the external 32.768khz crystal oscillator in HT66F0172. so the low speed oscillator for the HT66F0172 is only the internal 32khz (lirc) oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for the high speed and the low speed oscillators is chosen via configuration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. the osc1 and osc2 pins are used to connect the external components for the external crystal.
rev. 1.00 ?? ???? 11? ?01? rev. 1.00 ?? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu f h f h / 64 f h / ?? f h / 16 f h / 8 f h / 4 f h / ? 6 - stage presca?er f sub high speed osci??ation config?ration option f sys hlclk ? cks ? ~ cks 0 bits fast wake ?p from sleep mode or idle mode contro? ( for hxt on?? ) high speed osci??ation hxt hirc low speed osci??ation lxt lirc f l low speed osci??ation config?ration option note: there is not the lxt oscillator in HT66F0172 system clock confgurations external crystal/ceramic oscillator C hxt the external crystal/ ceramic system oscillator is one of the high frequency oscillator choices, which is selected via configuration option. for most crystal oscillator configurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation .
? ? ?? crystal/resonator oscillator C hxt crystal osillator c1 and c2 values crystal frequency c1 c2 1?mhz 0pf 0pf 8mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf note: c1 and c? va?es are for g?idance on?? . crystal recommended capacitor values
rev. 1.00 ?4 ???? 11? ?01? rev. 1.00 ?5 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has fxed frequency of 8mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 8mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pc0 and pc1 are free for use as normal i/o pins external 32 .768 khz crystal oscillator C l xt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specification. the external parallel feedback resistor, rp, is required. some confguration options determine if the xt1 and xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1 and xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1 and xt2 pins.
? ? ? ? ? ?- ? ? ? external lxt oscillator
rev. 1.00 ?4 ???? 11? ?01? rev. 1.00 ?5 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu lxt oscillator c1 and c2 values crystal frequency c1 c2 ??.768khz 10pf 10pf note: 1. c1 and c? va??es are for g?idance on?? . ?. r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values l xt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 q?ick start 1 low-power after power on , the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low- power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is a low frequency oscillator choice. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary clocks the low speed oscillator s , in addition to providing a system clock source are also used to provide a clock source to other device functions. these are the watchdog timer and the time base interrupt.
rev. 1.00 ?6 ???? 11? ?01? rev. 1.00 ?7 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either the hxt or the hirc oscillator , selected via a confguration option . the low speed system clock source can be sourced from either the lxt or the lirc oscillator , selected via a confguration option . but for HT66F0172, the low speed system clock source can only be sourced from the lirc oscillator. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the time base clock, f tbc . each of these internal clocks is sourced by either the lxt or lirc oscillators, selected via confguration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. f h f h / 64 f h / ?? f h / 16 f h / 8 f h / 4 f h / ? 6 - stage presca?er f sub high speed osci??ation config?ration option f sys hlclk ? cks ? ~ cks 0 bits fast wake - ?p from sleep mode or idle mode contro? ( for hxt on?? ) tbck time base wdt f tbc f tb f sys / 4 f s high speed osci??ation hxt hirc low speed osci??ation f l lxt lirc config?ration option low speed osci??ation system clock confgurations note: 1. when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. 2. there is not the lxt oscillator in HT66F0172
rev. 1.00 ?6 ???? 11? ?01? rev. 1.00 ?7 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep 0 , sleep 1 , idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f sub f s f tbc normal mode on f h ~f h /64 on on on slow mode on f l on on on i dl e0 mode off off on on on idle1 mode off on on on on sleep 0 mode off off off off off sleep 1 mode off off on on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillator. this mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator, either the hxt or hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from f l . running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep 0 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep 0 mode the cpu will be stopped. and the f sub and f s clocks will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to "0". if the lvden is set to "1", it wont enter the sleep0 mode . sleep 1 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep 1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the lvden is " 1" or the watchdog timer function is enabled. idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer and tms. in the idle0 mode, the system oscillator will be stopped.
rev. 1.00 ?8 ???? 11? ?01? rev. 1.00 ?9 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. control register a single register, smod, is used to overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7 ~ 5 cks2 ~ cks0: the system clock selection when hlclk is "0" 000: f l (f lxt or f lirc ) 001: f l (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc , a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten: fast wake-up control(only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f clock source is initially used after the device wakes up. when the bit is high, the f clock source can be used as a temporary system clock to provide a faster wake up time as the f clock is available. bit 3 lto: low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator sst ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 128 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 hto: high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator sst ready fag which indicates when the high speed system oscillator is stable after a wake-up has occurred. this fag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1 28 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the hirc oscillator is used.
rev. 1.00 ?8 ???? 11? ?01? rev. 1.00 ?9 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu bit 1 idlen: idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk: system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson: f sys control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as 0. bit 2 lvrf: lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low voltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf: lvrc control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program.
rev. 1.00 40 ???? 11? ?01? rev. 1.00 41 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilize and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast wake-up function has no effect because the f sub clock is stopped. the fast wake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscillator is selected as the normal mode system clock, and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 128 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator. if the hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycles of hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 1?8 hxt c ?c?es 1?8 hxt c ?c?es 1~? hxt c ?c?es 1 1?8 hxt c ?c?es 1~? f sub c?c?es (s?stem r?ns with f sub frst for 1?8 hxt c ?c?es and then switches over to r? n with the hxt c?ock) 1~? hxt c ?c?es hirc x 15~16 hirc c ?c ?es 15~16 hirc c?c?es 1~? hirc c?c?es lirc x 1~? lirc c?c?es 1~? lirc c?c?es 1~? lirc c?c?es lxt x 1 ?8 ltx c ?c?es 1~? lxt c ?c?es 1~? lxt c ?c?es wake-up times note that if the watchdog timer is disabled, which means that the lxt and lirc are both off, t hen there will be no fast wake-up function available when the device wakes-up from the sleep0 mode. operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/ slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register.
rev. 1.00 40 ???? 11? ?01? rev. 1.00 41 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms. the accompanying flowchart shows what happens when the device moves between the various operating modes.

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? normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by setting the hlclk bit to "0" and setting the cks2~cks0 bits to "000" or "001" in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc or the lxt oscillator and therefore requires th ese oscillator s to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "011", "100", "101", "110" or "111". as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
rev. 1.00 4? ???? 11? ?01? rev. 1.00 4? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu
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rev. 1.00 4? ???? 11? ?01? rev. 1.00 4? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu entering the sleep 0 mode there is only one way for the device to enter the sleep 0 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and time base clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the sleep 1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock will be stopped and the application program will stop at the "halt" instruction , but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enable d. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ctrl register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruc - tion, but the time base clock f tbc and f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared.
rev. 1.00 44 ???? 11? ?01? rev. 1.00 45 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ctrl register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the system clock and time base clock and f sub clock will be on and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to the device which has different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps .
rev. 1.00 44 ???? 11? ?01? rev. 1.00 45 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, i f the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, t he actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the "halt" instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the high speed and low speed oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hirc and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hirc oscillator has finished its sst period. ? if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after hto is "1". at this time, the lxt oscillator may not be stability if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is "1", the system clock can be switched to the lirc oscillator after wake up. ? there are peripheral functions for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change accord - ingly. ? the on/off condition of f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f s .
rev. 1.00 46 ???? 11? ?01? rev. 1.00 47 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal f s clock which is sourced from lxt or lirc oscillator chosen via a configuration option . the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lxt oscillator is supplied by an external 32.768khz crystal. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. note that the watchdog timer function is controlled by application program and is allowed to enable or disable wdt by application program. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable or disable operation. this register controls the overall operation of the watchdog timer. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we? we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~ 3 wdt function software control 10101: disabled 01010: enabled other: reset mcu when these bits are changed by the environmental noise to reset the microcontroller, the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1. bit 2~ 0 wdt time-out period selection 000: 2 8 / f s 001: 2 10 / f s 010: 2 12 / f s 011: 2 14 / f s 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period.
rev. 1.00 46 ???? 11? ?01? rev. 1.00 47 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 bit 7 fsyson: f control in idle mode describe elsewhere bit 6~ 3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag describe elsewhere bit 1 lrf: lvr control register software reset fag describe elsewhere bit 0 wrf: wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instruction will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. with regard to the watchdog timer enable/disable function, there are fve bits, we4~we0, in the wdtc register to offer additional enable or disable and reset control of the watchdog timer. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bits value is equal to 01010b. if the we4~we0 bits are set to any other values by the environmental noise, except 01010b and 10101b, it will reset the device after 2~3 lirc clock cycles. after power on these bits will have the value of 01010b. wdt function control we4 ~ we0 bits wdt function app?ication program enab?ed 10101b disab?e 01010b enab?e an? other va??e reset mcu watchdog timer enable/disable control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. several methods can be adopted to clear the contents of the watchdog timer. the frst is a wdt software reset, which means a certain value is written into the we4~we0 bit feld except 01010b and 10101b, the second is using the watchdog timer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer. that is to use the single "clr wdt" instruction to clear the wdt.
rev. 1.00 48 ???? 11? ?01? rev. 1.00 49 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. ? clr wdt ? instr?ction 8 - stage divider wdt presca?er we 4 ~ we 0 bits wdtc register reset mcu lxt f s f s / ? 8 8 -to -1 mux clr ws ? ~ ws 0 (f s / ? 8 ~ f s / ? 18 ) wdt time -o?t (? 8 / f s ~ ? 18 / f s ) lirc m u x low speed osci??ator config?ration option ? halt ? instr?ction watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are more than one way in which the microcontroller can be reset, each of which will be described as follows. power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. power-on reset timing chart
rev. 1.00 48 ???? 11? ?01? rev. 1.00 49 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the lvr function is always enabled with a specifc lvr voltage, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally and the lvrf bit in the ctrl register will also be set to 1. for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specifed in the lvd&lvr characteristics. if the low voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. t he actual v lvr value can be selected by the lvs 7~lvs0 bits in the lvrc register. if the lvs7~lvs0 bits are changed to some certain values by the environmental noise or software setting, the lvr will reset the device after 2~3 lirc clock cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the power down mode. low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 b it 7 ~ 0 lvr v oltage s elect control 01010101: 2. 1 v 00110011: 2.55v 10011001: 3.15 v 10101010: 3.8 v any other value: generates mcu reset C register is reset to por va??e when an actual low voltage condition occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles. in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned lvr values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation the register contents will be reset to the por value.
rev. 1.00 50 ???? 11? ?01? rev. 1.00 51 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu ? ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf w rf r/w r/w r/w r/w r/w por 0 0 0 b it 7 f sys control idle mode describe elsewhere bit 6~ 3 unimplemented, read as "0" bit 2 lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low voltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wdt control register software reset fag describe elsewhere watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware lvr reset except that the watchdog time-out fag to will be set to "1". wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to "0" and the to fag will be set to "1". refer to the a.c. characteristics for t sst details. wdt time-out reset during sleep or idle timing chart
rev. 1.00 50 ???? 11? ?01? rev. 1.00 51 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset ? ? lvr reset d ? ring normal or slow mode operation 1 ? wdt time-o ?t reset d? ring normal or slow mode operation 1 1 wdt time-o ?t reset d? ring idle or sleep mode operation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program co?nter reset to zero interr?pts a?? interr?pts wi?? be disab?ed wdt c?ear after reset? wdt begins co?nting timer mod ??es timer mod ??es wi?? be t? rned off inp?t/o?tp?t ports i/o ports wi?? be set?p as inp?ts stack pointer stack pointer wi?? point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register power on reset lvr reset wdt time-out (normal operation) wdt time-out (sleep/idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? mp1 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? bp ---- ---0 ---- ---0 ---- ---0 ---- ---? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? tbhp ---- -xxx ---- - ??? ---- - ??? ---- - ??? status --00 xxxx --?? xxxx --1? ???? --11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc --00 -000 --00 -000 --00 -000 --?? C??? integ ---- 0000 ---- 0000 ---- 0000 ---- ???? intc0 -0-0 0-00 -0-0 0-00 -0-0 0-00 -?-? ?-?? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc? --00 --00 --00 --00 --00 --00 --?? --?? mfi0 --00 --00 --00 --00 --00 --00 --?? --?? mfi1 --00 --00 --00 --00 --00 --00 --?? --?? mfi? --00 --00 --00 --00 --00 --00 --?? --??
rev. 1.00 5? ???? 11? ?01? rev. 1.00 5? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu register power on reset lvr reset wdt time-out (normal operation) wdt time-out (sleep/idle) pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pawu 0000 0000 0000 0000 0000 0000 ???? ???? tmpc 0--- --00 0--- --00 0--- --00 ? --- --?? wdtc 0101 0011 0101 0011 0101 0011 ???? ???? tbc 0011 0111 0011 0111 0011 0111 0011 0111 eea - - 00 0000 - - 00 0000 - - 00 0000 - - ?? ???? eed 0000 0000 0000 0000 0000 0000 ???? ???? adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- ???? ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- ???? adcr0 011 0 -000 011 0 -000 011 0 -000 ??? ? - ??? adcr1 00 - 0 - 000 00 - 0 - 000 00 - 0 - 000 ?? - ? - ??? acerl 1111 1111 1111 1111 1111 1111 ???? ???? ctrl 0--- -x00 0--- - 0 00 0--- - 0 00 ? --- -??? lvrc 0101 0101 0101 0101 0101 0101 ???? ???? tm0c0 0000 0 --- 0000 0 --- 0000 0 --- ???? ? --- tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? tm0dh 0000 0000 0000 0000 0000 0000 ???? ???? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah 0000 0000 0000 0000 0000 0000 ???? ???? tm0rpl 0000 0000 0000 0000 0000 0000 ???? ???? tm0rph 0000 0000 0000 0000 0000 0000 ???? ???? tm1c0 0000 0--- 0000 0--- 0000 0--- ???? ?--- tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh ---- -- 00 ---- -- 00 ---- -- 00 ---- -- ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah ---- -- 00 ---- -- 00 ---- -- 00 ---- -- ?? tm1rp l 0000 0000 0000 0000 0000 0000 ???? ???? tm1rph ---- -- 00 ---- -- 00 ---- -- 00 ---- -- ?? pc -- -- - 111 -- -- - 111 -- -- - 111 -- -- - ??? pcc -- -- - 111 -- -- - 111 -- -- - 111 -- -- - ??? pcpu ---- -000 ---- -000 ---- -000 -- -- - ??? pb - 111 1111 - 111 1111 - 111 1111 - ??? ???? pbc - 111 1111 - 111 1111 - 111 1111 - ??? ???? pbpu - 000 0000 - 000 0000 - 000 0000 - ??? ???? eec ---- 0000 ---- 0000 ---- 0000 ---- ???? note: " -" stands for " uni mplement ed " "u" stands for "unchanged" "x" stands for "unknown"
rev. 1.00 5? ???? 11? ?01? rev. 1.00 5? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa, pb and pc. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa d7 d6 d5 d4 d? d? d1 d0 pac d7 d6 d5 d4 d? d? d1 d0 papu d7 d6 d5 d4 d? d? d1 d0 pawu d7 d6 d5 d4 d? d? d1 d0 pb d6 d5 d4 d? d? d1 d0 pbc d6 d5 d4 d? d? d1 d0 pbpu d6 d5 d4 d? d? d1 d0 pc d? d1 d0 pcc d? d1 d0 pcpu d? d1 d0 i/o register list pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu~pcpu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit7~ bit 0 pull-high control 0: disable 1: enable
rev. 1.00 54 ???? 11? ?01? rev. 1.00 55 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu pbpu register bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 ~ 0 i/o port b bit 6 ~ bit 0 pull-high control 0: disable 1: enable pcpu register bit 7 6 5 4 3 2 1 0 name d? d1 d0 r/w r/w r/w r/w por 0 0 0 bit 7 ~ 3 unimplemented, read as "0" bit 2 ~ 0 i/o port c bit 2 ~ bit 0 pull-high control 0: disable 1: enable port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 wake up control 0: disable 1: enable
rev. 1.00 54 ???? 11? ?01? rev. 1.00 55 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu i/o port control registers each i/o port has its own control register known as pac~pcc, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 input/output control 0: output 1: input pbc register bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 bit 7 unimplemented, read as "0" bit 6 ~ 0 i/o port b bit 6 ~ bit 0 input/output control 0: output 1: input pcc register bit 7 6 5 4 3 2 1 0 name d? d1 d0 r/w r/w r/w r/w por 1 1 1 bit 7 ~ 3 unimplemented, read as "0" bit 2 ~ 0 i/o port c bit 2 ~bit 0 input/output control 0: output 1: input
rev. 1.00 56 ???? 11? ?01? rev. 1.00 57 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

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- ? ? ? ? ? ? a/d input/output structure
rev. 1.00 56 ???? 11? ?01? rev. 1.00 57 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac~pcc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa~pc, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. the power-on reset condition of the a/d converter control registers ensures that any a/d input pins - which are always shared with other i/o functions - will be setup as analog inputs after a reset. although these pins will be confgured as a/d inputs after a reset, the a/d converter will not be switched on. it is therefore important to note that if it is required to use these pins as i/o digital input pins or as other functions, the a/d converter control registers must be correctly programmed to remove the a/d function. note also that as the a/d channel is enabled, any internal pull-high resistor connections will be removed. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.00 58 ???? 11? ?01? rev. 1.00 59 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions the device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has two individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the tm type are described here with more detailed information provided in the individual periodic type tm section. introduction the device contains two tms having a reference name of tm0 and tm1. b oth of them are periodic type tm. the main features are summarised in the accompanying table. function ptm timer/co ?nter i/p capt ?re compare match o?tp?t pwm channe?s 1 sing?e p??se o?tp?t 1 pwm a ?ignment edge pwm adj ?stment period & d?t? d?t? or period ptm function summary tm0 tm1 10-bit p tm 1 0 -bit p tm tm name/type reference tm operation the type of tms offers a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting.
rev. 1.00 58 ???? 11? ?01? rev. 1.00 59 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu tm interrupts the type of tms has two internal interrupts, the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have an output pin. when the tm is in the compare match output mode, t he pin can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared functions is implemented using one register with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output if reset to zero the pin will retain its original other functions. tmpc register bit 7 6 5 4 3 2 1 0 name clop t1cp t 0 cp r/w r/w r/w r/w por 0 0 0 bit 7 control clo function to clo pin. 0: normal i/o 1: clo function bit 6 ~ 2 unimplemented, read as " 0 " bit 1 control tp1 function to tp1 pin. 0: normal i/o 1: tp1 function bit 0 control tp0 function to tp0 pin. 0: normal i/o 1: tp0 function
rev. 1.00 60 ???? 11? ?01? rev. 1.00 61 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu programming considerations the tm counter registers, the capture/compare ccra registers and ccrp registers, being 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra registers and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way described above, it is recommended to use the "mov" instruction to access the ccra or ccrp low byte registers, named tmxal or tmxrpl, using the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values.

? ? ? the following steps show the read and write procedures: ? writing data to ccra or ccr p ? step 1. write data to low byte tmxal or tmxrpl C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte tmxah or tmxrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccr p ? step 1. read data from the high byte tmxdh, tmxah or tmxrph C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxrpl C this step reads data from the 8-bit buffer.
rev. 1.00 60 ???? 11? ?01? rev. 1.00 61 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu periodic type tm C ptm the periodic type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the periodic tm can also be controlled with an external input pin and can drive one external output pin. periodic tm operation t he size of the two p-type tms is 10-bit wide. at the core is a 10 count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 10-bit wide. the only way of changing the value of the 10 -bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the p-type type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
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? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? periodic type tm block diagram (n=0, 1)
rev. 1.00 6? ???? 11? ?01? rev. 1.00 6? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu periodic type tm register description overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccr p value. the remaining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 tmnc0 tnpau tnck? tnck1 tnck0 tnon tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr tmndl d7 d6 d5 d4 d? d? d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d4 d? d? d1 d0 tmnah d9 d8 tmnrpl d7 d6 d5 d4 d? d? d1 d0 tmnrph d9 d8 10-bit periodic tm register list (n=0, 1) tm n c0 register bit 7 6 5 4 3 2 1 0 name t n pau t n ck? t n ck1 t n ck0 t n on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7 tm n counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. b it 6 ~ 4 select tm n counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: f h 110: tck n rising edge clock 111: tck n falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section.
rev. 1.00 6? ???? 11? ?01? rev. 1.00 6? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu b it 3 t n on: tm n counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tm output control bit, when the bit changes from low to high. b it 2 ~ 0 unimplemented, read as " 0 " name t n m1 t n m0 t n io1 t n io0 t n oc t n pol t n c apts t n cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 6 t n m1~t n m0: select tm n operat ion mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. b it 5 ~ 4 t n io1~t n io0: select tp n output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp n or tckn 01: input capture at falling edge of tp n or tckn 10: input capture at falling/rising edge of tp n or tckn 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.00 64 ???? 11? ?01? rev. 1.00 65 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the se bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t n on bit from low to high. in the pwm mode, the t n io1 and t n io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t n io1 and t n io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t n io1 and t n io0 bits are changed when the tm is running . b it 3 t n oc: tp n output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. b it 2 t n pol: tp n output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp n output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. b it 1 t n c apts : tm n capture trigger source select 0: from tp n pin 1: from tck n pin b it 0 t n cclr: select tm n counter clear condition 0: tm n compara tor p match 1: tm n compara tor a match this bit is used to select the method which clears the counter. remember that the periodic tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t n cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t n cclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.00 64 ???? 11? ?01? rev. 1.00 65 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~ 0 tm n counter low byte register bit 7 ~ bit 0 tm n 1 0 -bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 b it 7 ~ 2 unimplemented, read as "0" b it 1 ~ 0 tm n counter high byte register bit 1 ~ bit 0 tm n 10-bit counter bit 9 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 tm n ccra low byte register bit 7 ~ bit 0 tm n 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 b it 7 ~ 2 unimplemented, read as "0" b it 1 ~ 0 tm n ccra high byte register bit 1 ~ bit 0 tm n 10-bit ccra bit 9 ~ bit 8 tmnrpl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d? d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 tm n ccr p low byte register bit 7 ~ bit 0 tm n 10-bit ccr p bit 7 ~ bit 0
rev. 1.00 66 ???? 11? ?01? rev. 1.00 67 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu tmnrph register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7 ~ 2 unimplemented, read as "0" b it 1 ~ 0 tm n ccr p high byte register bit 1 ~ bit 0 tm n 10-bit ccr p bit 9 ~ bit 8 periodic type tm operating modes the periodic type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the t n m1 and t n m0 bits in the tm n c1 register. compare match output mode to select this mode, bits t n m1 and t n m0 in the tm n c1 register , should be all cleared to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the t n cclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both the t n af and t n pf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the t n cclr bit in the tm n c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the t n af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t n cclr is high no t n pf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to "0". as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t n af interrupt request fag is generated after a compare match occurs from comparator a. the t n pf interrupt request flag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the t n io1 and t n io0 bits in the tm n c1 register. the tm output pin can be selected using the t n io1 and t n io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the t n on bit changes from low to high, is setup using the t n oc bit. note that if the t n io1, t n io0 bits are zero then no pin change will take place.
rev. 1.00 66 ???? 11? ?01? rev. 1.00 67 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu co?nter va??e 0 x? ff ccrp ccra tnon tnpau tnpol ccrp int . f?ag tnpf ccra int . f?ag tnaf tm o / p pin time ccrp = 0 ccrp > 0 co?nter overf?ow ccrp > 0 co?nter c?eared b? ccrp va??e pa?se res?me stop co?nter restart tncclr = 0 ; tnm [ 1 : 0 ] = 00 o?tp?t pin set to initia? leve? low if tnoc = 0 o?tp?t togg?e with tnaf f?ag note tnio [ 1 : 0 ] = 10 active high o?tp?t se?ect here tnio [ 1 : 0 ] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnaf f?ag . remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin - shared f?nction o?tp?t inverts when tnpol is high compare match output mode C tncclr = 0 note: 1. with t n cclr = 0 C a comparator p match will clear the counter 2. the t m output pin is controlled only by the t n af fag 3. the o utput pin is reset to initial state by a t n on bit rising edge
rev. 1.00 68 ???? 11? ?01? rev. 1.00 69 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu co?nter va??e 0 x? ff ccrp ccra tnon tnpau tnpol ccrp int . f?ag tnpf ccra int . f?ag tnaf tm o / p pin time ccra = 0 ccra = 0 co?nter overf?ow ccra > 0 co?nter c?eared b? ccra va??e pa?se res?me stop co?nter restart tncclr = 1 ; tnm [ 1 : 0 ] = 00 o?tp?t pin set to initia? leve? low if tnoc = 0 o?tp?t togg?e with tnaf f?ag note tnio [ 1 : 0 ] = 10 active high o?tp?t se?ect here tnio [ 1 : 0 ] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnaf f?ag . remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin - shared f?nction o?tp?t inverts when tnpol is high tnpf not generated no tnaf f?ag generated on ccra overf?ow o?tp?t does not change compare match output mode C tncclr = 1 note: 1. with t n cclr = 1 C a comparator a match will clear the counter 2. the t m output pin is controlled only by the t n af fag 3. the output pin is reset to initial state by a t n on rising edge 4. the t n pf fag is not generated when t n cclr = 1
rev. 1.00 68 ???? 11? ?01? rev. 1.00 69 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu timer/counter mode to select this mode, bits t n m1 and t n m0 in the tm n c1 register should all be set to 11 respectively . the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits t n m1 and t n m0 in the tmnc1 register should be set to 10 respectively and also the t n io1 and t n io0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the t n cclr bit has no effect as the pwm period . both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the t n oc bit in the tm n c1 register is used to select the required polarity of the pwm waveform while the two t n io1 and t n io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t n pol bit is used to reverse the polarity of the pwm output waveform. 10-bit ptm, pwm mode , edge-aligned mode ccrp 1~1023 0000b period 1~10?? 10?4 d?t? ccra if f sys = 16mhz, tm clock source select f sys /4, ccrp = 512 and ccra = 128, the ptm pwm output frequency = (f sys /4) / (2256) = f sys /2048 = 7.8125khz, duty = 128/512 = 25% , if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.00 70 ???? 11? ?01? rev. 1.00 71 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu co?nter va??e ccrp ccra tnon tnpau tnpol ccrp int . f?ag tnpf ccra int . f?ag tnaf tm o / p pin ( tnoc = 1 ) time co?nter c?eared b? ccrp pa?se res?me co?nter stop if tnon bit ?ow co?nter reset when tnon ret?rns high tndpx = 0 ; tnm [ 1 : 0 ] = 10 pwm d?t? c?c?e set b? ccra pwm res?mes operation o?tp?t contro??ed b? other pin - shared f?nction o?tp?t inverts when tnpol = 1 pwm period set b? ccrp tm o / p pin ( tnoc = 0 ) pwm mode note: 1. here c ounter cleared by ccrp 2. a counter clear sets the pwm period 3 . the i nternal pwm function continues running even when t n io[1:0] = 00 or 01 4 . the t n cclr bit has no infuence on pwm operation single pulse mode to select this mode, the required bit pairs, t n m1 and t n m0 should be set to 10 respectively and also the corresponding t n io1 and t n io0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the t n on bit, which can be implemented using the application program. however in the single pulse mode, the t n on bit can also be made to automatically change from low to high using the external tck n pin, which will in turn initiate the single pulse output. when the t n on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the t n on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the t n on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the t n on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate tm interrupts. the counter can only be reset back to zero when the t n on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t n cclr bit is also not used.
rev. 1.00 70 ???? 11? ?01? rev. 1.00 71 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu

? ? ? ? ? ? ? ? ? ?? s ingle pulse generation co?nter va??e ccrp ccra tnon tnpau tnpol ccrp int . f?ag tnpf ccra int . f?ag tnaf tm o / p pin ( tnoc = 1 ) time co?nter stopped b? ccra pa?se res?me co?nter stops b? software co?nter reset when tnon ret?rns high tnm [ 1 : 0 ] = 10 ; tnio [ 1 : 0 ] = 11 p??se width set b? ccra o?tp?t inverts when tnpol = 1 no ccrp interr?pts generated tm o / p pin ( tnoc = 0 ) tckn pin software trigger c?eared b? ccra match tckn pin trigger a?to . set b? tckn pin software trigger software c?ear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tck n pin or by setting the t n on bit high 4. a tck n pin active edge will automatically set the t n on bit high 5. in the single pulse mode, t n io [1:0] must be set to "11" and can not be changed. capture input mode to select this mode bits t n m1 and t n m0 in the tm n c1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tp n or tckn pin , selected by the t n capts bit in the tm n c0 register. the input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the t n io1 and t n io0 bits in the tm n c1 register. the counter is started when the t n on bit changes from low to high which is initiated using the application program.
rev. 1.00 7? ???? 11? ?01? rev. 1.00 7? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu when the required edge transition appears on the tp n or t ckn pin the present value in the counter will be latched into the ccra register and a tm interrupt generated. irrespective of what events occur on the tp n or t ckn pin the counter will continue to free run until the t n on bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the t n io1 and t n io0 bits can select the active trigger edge on the tp n or t ckn pin to be a rising edge, falling edge or both edge types. if the t n io1 and t n io0 bits are both set high, then no capture operation will take place irrespective of what happens on the tp n or t ckn pin, however it must be noted that the counter will continue to run. as the tp n or tck n pin is pin shared with other functions, care must be taken if the tm n is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the t n cclr, t n oc and t n pol bits are not used in this mode. co?nter va??e yy ccrp tnon tnpau ccrp int . f?ag tnpf ccra int . f?ag tnaf ccra va??e time co?nter c?eared b? ccrp pa?se res?me co?nter reset tnm [ 1 : 0 ] = 01 tm capt?re pin tpn or tckn xx co?nter stop tnio [ 1 : 0 ] va??e xx yy xx yy active edge active edge active edge 00 ? rising edge 01 ? fa??ing edge 10 ? both edges 11 ? disab?e capt?re capt?re inp?t mode note: 1. t n m [1:0] = 01 and active edge set by the t n io[1:0] bits 2. a tm capture input pin active edge transfers counter value to ccra 3. the t n cclr bit is not used 4. no output function C t n oc and t n pol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero
rev. 1.00 7? ???? 11? ?01? rev. 1.00 7? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview this device contains a multi -channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 1 2 -bit digital value. input channels a/d channel select bits input pins 8 acs4? acs?~acs0 an0~an 7 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers.

? ? ? ?? ? ?? ?? ? ?? ?? - ? - ?? ? ?
? ? ? ? ? ? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? a/d converter structure a/d converter register description overall operation of the a/d converter is controlled using fve registers. a read only register pair adrl/adrh exists to store the adc data 12-bit value. the remaining three registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 adrl (adrfs=0) d ? d ? d 1 d 0 adr l(adrfs=1) d 7 d 6 d 5 d 4 d ? d ? d 1 d 0 adr h(adrfs=0) d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 adr h(adrfs=1) d 11 d 10 d 9 d 8 adcr 0 start eocb adoff adrfs acs? acs1 acs0 adcr1 acs4 v1?5en vrefs adck? adck1 adck0 acerl ace7 ace6 ace5 ace4 ace? ace? ace1 ace0 a/d converter register list
rev. 1.00 74 ???? 11? ?01? rev. 1.00 75 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu a/d converter data registers C adrl, adrh as this device contains an internal 1 2 -bit a/d converter, it requires two data registers to store the converted value. these are a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d? d? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d? d? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, a cerl to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 and a cerl are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/ d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs2~acs0 bits in the adcr0 register define the adc input channel number. as the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter. it is the function of the acs4 and acs2~acs0 bits to determine which analog channel input pins or 1.25v is actually connected to the internal a/d converter. the acerl control register contains the ace 7 ~ace0 bits which determine which pins are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.00 74 ???? 11? ?01? rev. 1.00 75 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu adcr0 register bit 7 6 5 4 3 2 1 0 name start eocb adoff adrfs acs? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 bit 7 start : start the a/d conversion 010: start 01: reset the a/d converter and set eocb to "1"this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : adc data format control 0: a/d data msb is adrh bit 7, lsb is adrl bit 4 1: a/d data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 unimplemented, read as "0" bit 2 ~ 0 acs2 ~ acs0: select a/d channel (when acs4 is " 0 " ) 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter.
rev. 1.00 76 ???? 11? ?01? rev. 1.00 77 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu adcr1 register bit 7 6 5 4 3 2 1 0 name acs4 v1?5en vrefs adck? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4 : select internal 1.25v as adc input control 0: disable 1: enable this bit enables 1.25v to be connected to the a/d converter. the v125en bit must frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v125en : internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/off function to the a/d converter. when the bit is set high the bandgap voltage 1.25v can be used by the a/d converter. if 1.25v is not used by the a/d converter and the lvr/lvd function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. when 1.25v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as "0" bit 4 vrefs : select adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter. if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. when the a/d converter reference voltage is supplied on the external vref pin which is pin-shared with other functions, all of the pin-shared functions except vref on this pin are disabled. bit3 unimplemented, read as "0" bit 2 ~ 0 adck2 ~ adck0: select adc clock source 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: undefned these three bits are used to select the clock source for the a/d converter.
rev. 1.00 76 ???? 11? ?01? rev. 1.00 77 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu acerl register bit 7 6 5 4 3 2 1 0 name ace7 ace6 ace5 ace4 ace? ace? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace7 : defne pb3 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6 : defne pa7 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5 : defne pa6 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ace4 : defne pa5 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pa4 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pb2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pb1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pb0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d operation the start bit in the adcr0 register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr0 register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically set to "0" by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f , can be chosen to be either f or a subdivided version of f . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/d clock source is determined by the system clock, f , and by bits adck2~adck0, there are some limitations on the maximum a/ d clock source speed that can be selected. as the recommended range of permissible a/d clock
rev. 1.00 78 ???? 11? ?01? rev. 1.00 79 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu period, tadck, is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 110b. doing so will give a/d clock periods that are less than the minimum a/ d clock period or greater than the maximum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t ad ck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1 mhz 1s ? s 4 s 8 s 16 s* ?? s* 64 s* undefned ? mhz 5 00ns 1s ? s 4 s 8 s 16 s* ?? s* undefned 4 mhz ? 5 0ns* 5 00ns 1s ? s 4 s 8 s 16 s* undefned 8 mhz 1 ?5 ns* ? 5 0ns* 5 00ns 1s ? s 4 s 8 s undefned 1? mhz 8? ns* 1 67 ns* ??? ns* 667 ns* 1 .?? s ?.67 s 5.?? s undefned a/d clock period examples controlling the power on/off function of the a/d converter circuitry is implemented using the adoff bit in the adcr0 register. this bit must be zero to power on the a/d converter. when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace 7 ~ace0 bits in the acerl registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, avdd, or from an external reference sources supplied on pin vref. the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a as well as other functions. the ace 7 ~ ace0 bits in the acerl registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace 7 ~ ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pac or pbc port control register s to enable the a/d input as when the ace 7 ~ ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref .
rev. 1.00 78 ???? 11? ?01? rev. 1.00 79 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu
? ? ? ? ?? ? ? - a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4, acs2~acs0 bits which are also contained in the adcr1 and adcr0 register s . ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace7~ace0 bits in the acerl register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 6 t he analog to digital conversion process can now be initialised by setting the start bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data register adrl and adrh can be read to obtain the conversion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t adck where t adck is equal to the a/d clock period.
rev. 1.00 80 ???? 11? ?01? rev. 1.00 81 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu

? ? ? ? ? ? ? ? ? ? ? - ?? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ? ? a/d conversion timing programming considerations during microcontroller operations where the a/d converter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by setting bit adoff high in the adcr0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contains a 1 2 -bit a/d converter, its full-scale converted digitised value is equal to f ffh. since the full-scale analog input value is equal to the v dd voltage, this gives a single bit analog input value of a v dd or v ref divided by 4096 . 1 lsb= (v dd or v ref ) / 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) / 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the a v dd or v ref level.

? ? ? ? ? ? ?? ? ?
? ideal a/d transfer function
rev. 1.00 80 ???? 11? ?01? rev. 1.00 81 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a, 03h mov adcr1, a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a, f fh ; setup acerl to confgure pins an0~an 7 mov acerl, a mov a, 00h mov adcr0, a ; enable and connect an0 channel to a/d converter : : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a, adrl ; read low byte conversion result value mov adrl_buffer, a ; save result to user defned register mov a, adrh ; read high byte conversion result value mov adrh_buffer, a ; save result to user defned register : jmp start_conversion ; start next a/d conversion note: to power off the adc, it is necessary to set adoff as "1".
rev. 1.00 8? ???? 11? ?01? rev. 1.00 8? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a, 03h mov adcr1, a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a, f fh ; setup acerl to confgure pins an0~an 7 mov acerl, a mov a, 00h mov adcr0, a ; enable and connect an0 channel to a/d converter : : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_: mov acc_stack, a ; save acc to user defned memory mov a, status mov status_stack, a ; save status to user defned memory : : mov a, adrl ; read low byte conversion result value mov adrl_buffer, a ; save result to user defned register mov a, adrh ; read high byte conversion result value mov adrh_buffer, a ; save result to user defned register : : exit_isr: mov a, status_stack mov status, a ; restore status from user defned memory mov a, acc_stack ; restore acc from user defned memory clr adf ; clear adc interrupt fag reti note: to power off the adc, it is necessary to set adoff as "1".
rev. 1.00 8? ???? 11? ?01? rev. 1.00 8? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int0 and int1 pins, while the internal interrupts are generated by various internal functions such as the tms, time base, lvd, eeprom and the a/d converter. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi 2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/disable bit or "f" for request fag. function enable bit request flag notes g?oba? emi intn pin intne intnf n=0 or 1 m??ti-f?nction mfne mfnf n=0~? time base tb n e tb n f n=0 or 1 a/d converter a d e a d f lvd lve lvf eeprom write de e de f p tm tnae tnaf n=0 or 1 tnpe tnpf interrupt register bit naming conventions name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ int 1 s1 int 1 s0 int 0 s1 int 0 s0 intc0 mf 0f int0f mf0e int0e emi intc1 tb0 f adf mf?f mf1f tb0e ade mf?e mf1e intc? int1f tb1f int1e tb1e mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi? def lvf dee lve interrupt register contents C ht66f0174
rev. 1.00 84 ???? 11? ?01? rev. 1.00 85 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 mf0f int0f mf0e int0e emi intc1 tb0f adf mf?f mf1f tb0e ade mf?e mf1e intc? int1f tb1f int1e tb1e mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi? lvf lve interrupt register contents C ht66f017 2 integ register bit 7 6 5 4 3 2 1 0 name int 1 s1 int 1 s0 int 0 s1 int 0 s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~4 unimplemented, read as "0" bit 3~2 int 1 s1, int 1 s0: interrupt edge control for int1 pin 00 : disable 01 : rising edge 10 : falling edge 11 : dual edge bit 1~0 int 0 s1, int 0 s0: interrupt edge control for int 0 pin 00 : disable 01 : rising edge 10 : falling edge 11 : dual edge intc0 register bit 7 6 5 4 3 2 1 0 name mf 0f int0f mf0e int0e emi r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 mf 0f: multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 5 unimplemented, read as "0" bit 4 int0 f: int0 interrupt request flag 0: no request 1: interrupt request bit 3 mf 0e: multi-function interrupt 0 control 0: disable 1: enable bit 2 unimplemented, read as "0" bit 1 int0 e: int0 interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable
rev. 1.00 84 ???? 11? ?01? rev. 1.00 85 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu intc1 register bit 7 6 5 4 3 2 1 0 name tb0f adf mf?f mf1f tb0e ade mf?e mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb0 f : time base 0 interrupt request flag 0: no request 1: interrupt request bit 6 adf: a/d converter interrupt request flag 0: no request 1: interrupt request bit 5 mf 2 f: multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 4 mf 1 f: multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 3 tb0 e : time base 0 interrupt control 0: disable 1: enable bit 2 a de: a/d converter interrupt control 0: disable 1: enable bit 1 mf 2 e: multi-function interrupt 2 control 0: disable 1: enable bit 0 mf1e: multi-function interrupt 1 control 0: disable 1: enable intc2 register bit 7 6 5 4 3 2 1 0 name int1f tb1f int1e tb1e r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~6 unimplemented, read as "0" bit 5 int1 f: int1 interrupt request flag 0: no request 1: interrupt request bit 4 tb1 f: time base 1 interrupt request flag 0: no request 1: interrupt request bit 3 ~2 unimplemented, read as "0" bit 1 int1 e: int1 interrupt control 0: disable 1: enable bit 0 tb1 e: time base 1 interrupt control 0: disable 1: enable
rev. 1.00 86 ???? 11? ?01? rev. 1.00 87 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu mfi0 register bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe: tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 name t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t1af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe: tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 86 ???? 11? ?01? rev. 1.00 87 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu mfi2 register C ht66f0174 bit 7 6 5 4 3 2 1 0 name def lvf dee lve r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 def: data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf: lvd interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 dee: data eeprom interrupt control 0: disable 1: enable bit 0 lve: lvd interrupt control 0: disable 1: enable mfi2 register C HT66F0172 bit 7 6 5 4 3 2 1 0 name lvf lve r/w r/w r/w por 0 0 bit 7~5 unimplemented, read as "0" bit 4 lvf: lvd interrupt request fag 0: no request 1: interrupt request bit 3~1 unimplemented, read as "0" bit 0 lve: lvd interrupt control 0: disable 1: enable
rev. 1.00 88 ???? 11? ?01? rev. 1.00 89 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu interrupt operation when the conditions for an interrupt event occur, such as a tm compare p or compare a match or a/d conversion completion etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a "jmp" which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti", which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request fags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. int 0 pin int 1 pin int0 f int1 f int0 e int1 e emi 04 h emi 0 ch emi 10 h time base 0 tb 0 f tb 0 e emi 1 ch interrupt name request flags enable bits master enable vector emi auto disabled in isr priority high low tm 0 p t0 pf t 0 pe tm 0 a t0 af t 0 ae m . funct . 0 mf 0 f mf 0 e interrupts contained within multi - function interrupts xxe enable bits xxf request flag , auto reset in isr legend xxf request flag , no auto reset in isr emi 20 h emi 24 h m . funct . 1 mf 1 f mf 1 e time base 1 tb 1 f tb 1 e a / d adf ade emi 18 h emi 14 h lvd lvf lve m . funct . 2 mf 2 f mf 2 e eeprom def dee tm 1 p t1 pf t 1 pe tm 1 a t1 af t 1 ae interrupt structure C ht66f0174
rev. 1.00 88 ???? 11? ?01? rev. 1.00 89 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu int 0 pin int 1 pin int 0 f int 1 f int 0 e int 1 e emi 04 h emi 0 ch emi 10 h time base 0 tb 0 f tb 0 e emi 1 ch interr?pt name req?est f?ags enab?e bits master enab?e vector emi a?to disab?ed in isr priorit? high low tm 0 p t 0 pf t 0 pe tm 0 a t 0 af t 0 ae m. f?nct . 0 mf 0 f mf 0 e interr?pts contained within m??ti - f?nction interr?pts xxe enab?e bits xxf req?est f?ag ? a?to reset in isr legend xxf req?est f?ag ? no a?to reset in isr emi ?0 h emi ?4 h m. f?nct . 1 mf 1 f mf 1 e time base 1 tb 1 f tb 1 e a/ d adf ade emi 18 h emi 14 h lvd lvf lve m. f?nct . ? mf ? f mf ? e tm 1 p t 1 pf t 1 pe tm 1 a t 1 af t 1 ae interrupt structure C HT66F0172 external interrupt the external interrupts are controlled by signal transitions on the pins int0, int1. an external interrupt request will take place when the external interrupt request fags, int0f, int1f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e, int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request flags, int0f, int1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull- high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function.
rev. 1.00 90 ???? 11? ?01? rev. 1.00 91 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu time base interrupt the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section. tbc register C ht66f0174 bit 7 6 5 4 3 2 1 0 name tbon tbck tb 1 1 tb 1 0 lxtlp tb0? tb 0 1 tb 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon: tb0 and tb1 c o ntrol 0: disable 1: enable bit 6 tbck: select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb1 1 ~tb 1 0: select time base 1 time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp : lxt low power control 0: d isable 1: e nable bit 2~0 tb02 ~ tb00: select time base 0 time-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb
rev. 1.00 90 ???? 11? ?01? rev. 1.00 91 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu tbc register C HT66F0172 bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 tb0? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon: tb0 and tb1 control 0: disable 1: enable bit 6 tbck: select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10: select time base 1 time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 unimplemented, read as "0" bit 2~0 tb02~tb00: select time base 0 time-out period 000 : 256/ f tb 001 : 512/ f tb 010 : 1024/ f tb 011 : 2048/ f tb 100 : 4096/ f tb 101 : 8192/ f tb 110 : 16384/ f tb 111: 32768/ f tb
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time base interrupt multi-function interrupt within the device there are up to three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, lvd interrupt and eeprom interrupt. a multi- function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag and the corresponding interrupt enable bit must be set. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi- function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt fags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi- function interrupts, namely the p tm interrupts, lvd interrupt and eeprom interrupt will not be automatically reset and must be manually reset by the application program.
rev. 1.00 9? ???? 11? ?01? rev. 1.00 9? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu a/d converter interrupt the device contains an a/d converter which has its own independent interrupt. the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt flag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. tm interrupt the periodic type tms have two interrupts each. all of the tm interrupts are contained within the multi-function interrupts. for each of the periodic type tms there are two interrupt request fags, tnpf and tnaf, and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags is set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. eeprom interrupt (only for HT66F0172) the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def, is set, which occurs when an eeprom write cycle ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle ends, a subroutine call to the respective eeprom interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however, only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. a lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the lvf fag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.00 9? ???? 11? ?01? rev. 1.00 9? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt f ag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request fags, mf0f~mf2f, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts .
rev. 1.00 94 ???? 11? ?01? rev. 1.00 95 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu low voltage detector C lvd the device has a low voltage detector function, also known as lvd. this enables the device to monitor the power supply voltage, v dd , and provides a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be dete r mined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 lvdo: lvd output flag 0: no low voltage detect 1: low voltage detect bit 4 lvden: low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vlvd2 ~ vlvd0: select lvd voltage 000: 2.0 v 001: 2.2 v 010: 2.4 v 011: 2.7 v 100: 3.0 v 101: 3.3 v 110: 3.6v 111: 4.0 v
rev. 1.00 94 ???? 11? ?01? rev. 1.00 95 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.0v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low voltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.00 96 ???? 11? ?01? rev. 1.00 97 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu confguration option confguration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed s?stem osci??ator se?ection C f h : 1. hxt ?. hirc ? low speed s?stem osci??ator se?ection C f l : 1. lxt ?. lirc note: the HT66F0172 doesn't have the lxt oscillator, so the low speed system oscillator for HT66F0172 is only lirc. application circuits

rev. 1.00 96 ???? 11? ?01? rev. 1.00 97 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 98 ???? 11? ?01? rev. 1.00 99 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction "ret" in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "halt" instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 98 ???? 11? ?01? rev. 1.00 99 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[m] add data memor? to acc 1 z? c? ac? ov addm a?[m] add acc to data memor ? 1 note z? c? ac? ov add a?x add immediate data to acc 1 z? c? ac? ov adc a?[m] add data memor? to acc with carr? 1 z? c? ac? ov adcm a?[m] add acc to data memor ? with carr? 1 note z? c? ac? ov sub a?x s? btract immediate data from the acc 1 z? c? ac? ov sub a?[m] s?btract data memor? from acc 1 z? c? ac? ov subm a?[m] s?btract data memor? from acc with res??t in data memor? 1 note z? c? ac? ov sbc a?[m] s?btract data memor? from acc with carr? 1 z? c? ac? ov sbcm a?[m] s?btract data memor? from acc with carr ?? res??t in data memor? 1 note z? c? ac? ov daa [m] decima? adj? st acc for addition with res??t in data memor? 1 note c logic operation and a?[m] logica? and data memor? to acc 1 z or a?[m] logica? or data memor? to acc 1 z xor a?[m] logica? xor data memor? to acc 1 z andm a?[m] logica? and acc to data memor? 1 note z orm a?[m] logica? or acc to data memor? 1 note z xorm a?[m] logica? xor acc to data memor? 1 note z and a?x logica? and immediate data to acc 1 z or a?x logica? or immediate data to acc 1 z xor a?x logica? xor immediate data to acc 1 z cpl [m] comp?ement data memor? 1 note z cpla [m] comp?ement data memor? with res?? t in acc 1 z increment & decrement inca [m] increment data memor? with res?? t in acc 1 z inc [m] increment data memor? 1 note z deca [m] decrement data memor? with res?? t in acc 1 z dec [m] decrement data memor? 1 note z rotate rra [m] rotate data memor? right with res?? t in acc 1 none rr [m] rotate data memor? right 1 note none rrca [m] rotate data memor? right thro?gh carr? with res?? t in acc 1 c rrc [m] rotate data memor? right thro?gh carr? 1 note c rla [m] rotate data memor? ?eft with res?? t in acc 1 none rl [m] rotate data memor? ?eft 1 note none rlca [m] rotate data memor? ?eft thro?gh carr? with res?? t in acc 1 c rlc [m] rotate data memor? ?eft thro?gh carr? 1 note c
rev. 1.00 100 ???? 11? ?01? rev. 1.00 101 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu mnemonic description cycles flag affected data move mov a ?[m] move data memor? to acc 1 none mov [m]?a move acc to data memor ? 1 note none mov a ?x move immediate data to acc 1 none bit operation clr [m].i c?ear bit of data memor? 1 note none set [m].i set bit of data memor? 1 note none branch ? mp addr ??mp ?nconditiona??? ? none sz [m] skip if data memor? is zero 1 note none sza [m] skip if data memor? is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memor? is zero 1 note none snz [m].i skip if bit i of data memor? is not zero 1 note none siz [m] skip if increment data memor? is zero 1 note none sdz [m] skip if decrement data memor? is zero 1 note none siza [m] skip if increment data memor? is zero with res?? t in acc 1 note none sdza [m] skip if decrement data memor? is zero with res?? t in acc 1 note none call addr s?bro?tine ca?? ? none ret ret?rn from s?bro?tine ? none ret a ?x ret?rn from s?bro?tine and ? oad immediate data to acc ? none reti ret?rn from interr?pt ? none table read tabrd [m] read tab? e to tblh and data memor? ? note none tabrdl [m] read tab?e (? ast page) to tblh and data memor? ? note none miscellaneous nop no operation 1 none clr [m] c?ear data memor? 1 note none set [m] set data memor? 1 note none clr wdt c? ear watchdog timer 1 to ? pdf clr wdt1 pre-c? ear watchdog timer 1 to ? pdf clr wdt? pre-c? ear watchdog timer 1 to ? pdf swap [m] swap nibb?es of data memor? 1 note none swapa [m] swap nibb?es of data memor? with res?? t in acc 1 none halt enter power down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.00 100 ???? 11? ?01? rev. 1.00 101 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu instruction defnition adc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. operation acc acc + x affected fag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specifed immediate data perform a bit wise logical and operation. the result is stored in the accumulator. operation acc acc and x affected fag(s) z andm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z
rev. 1.00 10? ???? 11? ?01? rev. 1.00 10? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu call addr subroutine call description unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specifed address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. operation stack program counter + 1 program counter addr affected fag(s) none clr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none clr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none clr wdt clear watchdog timer description the to, pdf fags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt2 and must be executed alternately with clr wdt2 to have effect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed alternately with clr wdt1 to have effect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf cpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z
rev. 1.00 10? ???? 11? ?01? rev. 1.00 10? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu cpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c dec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down fag pdf is set and the wdt time-out fag to is cleared. operation to 0 pdf 1 affected fag(s) to, pdf inc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.00 104 ???? 11? ?01? rev. 1.00 105 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu jmp addr jump unconditionally description the contents of the program counter are replaced with the specifed address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected fag(s) none mov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none mov a,x move immediate data to acc description the immediate data specifed is loaded into the accumulator. operation acc x affected fag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected fag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z or a,x logical or immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected fag(s) z orm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the restored address. operation program counter stack affected fag(s) none
rev. 1.00 104 ???? 11? ?01? rev. 1.00 105 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. operation program counter stack acc x affected fag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected fag(s) none rl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none rla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none rlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c rr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none
rev. 1.00 106 ???? 11? ?01? rev. 1.00 107 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu rra [m] rotate data memory right with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none rrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c sbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none
rev. 1.00 106 ???? 11? ?01? rev. 1.00 107 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none set [m] set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none set [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none sub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c
rev. 1.00 108 ???? 11? ?01? rev. 1.00 109 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu subm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? x affected fag(s) ov, z, ac, c swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none sz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none
rev. 1.00 108 ???? 11? ?01? rev. 1.00 109 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu tabrd [m] read table (current page) to tblh and data memory description the low byte of the program code addressed by the table pointer (tbhp and tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z xorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected fag(s) z
rev. 1.00 110 ???? 11? ?01? rev. 1.00 111 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information ? pb free products ? green packages products
rev. 1.00 110 ???? 11? ?01? rev. 1.00 111 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu 20-pin dip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages see fig1 symbol dimensions in inch min. nom. max. a 0.980 1.060 b 0.?40 0.?80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0?? f 0.045 0.070 g 0.100 h 0.?00 0.??5 i 0.4?0 symbol dimensions in mm min. nom. max. a ?4.89 ?6.9? b 6.10 7.11 c ?.9? 4.95 d ?.9? ?.81 e 0.?6 0.56 f 1.14 1.78 g ?.54 h 7.6? 8.?6 i 10.9?
rev. 1.00 11 ? ???? 11? ?01? rev. 1.00 11 ? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu see fig2 symbol dimensions in inch min. nom. max. a 0.945 0.985 b 0.?75 0.?95 c 0.1?0 0.150 d 0.110 0.150 e 0.014 0.0?? f 0.045 0.060 g 0.100 h 0.?00 0.??5 i 0.4?0 symbol dimensions in mm min. nom. max. a ?4.00 ?5.0? b 6.99 7.49 c ?.05 ?.81 d ?.79 ?.81 e 0.?6 0.56 f 1.14 1.5? g ?.54 h 7.6? 8.?6 i 10.9?
rev. 1.00 11 ? ???? 11? ?01? rev. 1.00 11 ? ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu 20-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.?9? 0.419 b 0.?56 0.?00 c 0.01? 0.0?0 c 0.496 0.51? d 0.104 e 0.050 f 0.004 0.01? g 0.016 0.050 h 0.008 0.01? 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.6? c 0.?0 0.51 c 1?.60 1?.00 d ?.64 e 1.?7 f 0.10 0.?0 g 0.41 1.?7 h 0.?0 0.?? 0 8
rev. 1.00 114 ???? 11? ?01? rev. 1.00 115 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.??8 0.?44 b 0.150 0.158 c 0.008 0.01? c 0.??5 0.?47 d 0.049 0.065 e 0.0?5 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.?0 b ?.81 4.01 c 0.?0 0.?0 c 8.51 8.81 d 1.?4 1.65 e 0.64 f 0.10 0.?5 g 0.?8 1.?7 h 0.18 0.?5 0 8
rev. 1.00 114 ???? 11? ?01? rev. 1.00 115 ???? 11? ?01? HT66F0172/ht66f0174 enhanced a/d flash 8-bit mcu cop?right ? ?01? b? holtek semiconductor inc. the information appearing in this data sheet is be ?ieved to be acc? rate at the time of p ?b? ication. however ? ho? tek ass? mes no responsibi?it? arising from the ? se of the specifcations described. the applications mentioned herein are used solely for the p?rpose of i???stration and ho?tek makes no warrant? or representation that s? ch app? ications wi?? be s?itab?e witho? t f? rther modification? nor recommends the ?se of its prod?cts for app?ication that ma? present a risk to h?man ?ife d?e to ma?f ? nction or otherwise. ho?tek's prod? cts are not a? thorized for ? se as critica? components in ?ife s?pport devices or s?stems. ho?tek reserves the right to a?ter its products without prior notifcation. for the most up-to-date information, please visit o? r web site at http://www.ho? tek.com.tw.

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